1. Field of the Invention
The invention relates to biasing of CMOS circuits, and more particularly to avoiding problems with biasing, current mismatch, low transconductance, and sizing of circuits in the weak inversion region.
2. Description of the Related Art
It is well known that the main hurdle for low voltage (1.5V and below) circuit operation is the metal oxide semiconductor (MOS) transistor threshold voltage. Fortunately there exists a region of operation for the MOS transistor which allows low voltage operation. This is the so-called "sub-threshold" or "weak inversion" region. In this region, the transistor can be made to operate at a gate-source voltage of about 200 mV below the threshold voltage as compared to about 200 mV above it for the normal or the "strong inversion" region of operation. Also, the drain current saturation voltage in weak inversion region is also low--less than 100 mV compared to typically 200 mV for strong inversion. Therefore it is easy to see that the weak inversion region of operation provides opportunities for designing low voltage circuits.
FIG. 1a shows a conventional prior art current mirror in strong inversion with unequal sized transistors. The drain and source of an n-channel transistor NR0 are shown connected between a current supply I.sub.-- IN and the gate is shown connected to the drain, creating a current source. N-channel transistor NR1 has its drain and source connected between I.sub.-- OUT and ground, and its gate is connected to the gate of transistor NR0. NR1, thus acts as a current mirror, conducting a current of n times the current I flowing into transistor NR0, because NR1 has a width n times wider than transistor NR0.
FIG. 2a shows a conventional prior art common source amplifier in strong inversion. P-channel transistors PR0 and PR1 act as a current source/mirror, similar to transistors NR0 and NR1 of FIG. 1a. PR1 supplies a current I to output OUT, equal to the current flowing through PRO to input IBIAS.sub.-- IN. N-channel transistor NR1, the common source amplifier, is connected between output OUT and ground and receives at its gate a bias voltage and signal input BIAS+SIGNAL which is to be amplified. R.sub.o is the resistance seen at the output. The voltage gain is given by: ##EQU1## where g.sub.m1 =transconductance of NR1 R.sub.o output resistance of PR1 and NR1 in parallel.
FIG. 3 shows a prior art differential input amplifier in strong inversion. The current mirror is identical to the one of FIG. 2a, except that PR1, the current mirror, has twice the width of PRO to deliver twice the current (2I) of PR0. The differential amplifier consists of differential inputs INP and INM which each feed the p-channel transistor gate of a first and second CMOS circuit comprised of PRA1/NRA1 and PRB1/NRB1, respectively. NRA1 is a current source for current mirror NRB1. Each string PRA1/NRA1 and PRB1/NRB1 conduct current I. The output OUT has an output resistance of R.sub.o. The voltage gain is given by: ##EQU2## where gm.sub.1 =transconductance of PRB1 R.sub.o =output resistance of PRB1 and NRB1 in parallel.
The problems associated with weak inversion operation are firstly, absence of a design guideline for biasing the transistor in the correct region of operation, secondly the drain current mismatch for unequal sized current mirrors and thirdly very low transconductance and current driving capabilities. All these problems are resolved in the invention maintaining requirements of low voltage operation.
There are two papers which treat the subject of weak inversion operation. The first paper is by Eric Vittoz and Jean Fellrath, titled CMOS Analog Integrated Circuits Based on Weak Inversion Operation, IEEE Journal of Solid-State Circuits, Vol. SC-12, NO. 3, June 1977. The second paper is by Tim Grotjohn and Bernd Hoefflinger, titled A Parametric Short-Channel MOS Transistor Model for Subthreshold and Strong Inversion Current, IEEE Journal of Solid-State Circuits, Vol. SC-19, NO. 1. February 1984.
The following three U.S. Patents have come to our attention which utilize circuits that use biasing in the weak inversion region. U.S. Pat. No. 5,047,706 (Ishibashi et al.) describes a constant current, constant voltage circuit in which two of the MOS devices are operated in a sub-threshold region, however, there does not appear to be any discussion of the invention's deviation in output current. U.S. Pat. No. 4,792,749 (Kitagawa et al.) describes a voltage regulator for a solar cell in which a CMOS current mirror is operated in the weak inversion region. U.S. Pat. No. 4,555,623 (Bridgewater et al.) discloses a pre-amplifier for a focal plane detector array in which the devices are operated in a weak inversion region.
It should be noted that none of the above-cited examples of the related art provide multiple unit sized CMOS transistors avoiding threshold voltage mismatch and deviation of the output current.